With miniaturization of semiconductor elements, it is becoming increasingly difficult to form patterns the same as in a design layout on a substrate such as a wafer. One of the reasons is that the improvement in resolution of exposure devices has not caught up with advances in miniaturization of semiconductor elements so that the transfer qualities of patterns in a lithography process are deteriorated increasingly.
Quality deterioration patterns (error patterns), which demonstrate a significant reduction in the transfer quality, have a tremendous influence on the production yield. As a matter of fact, even if patterns comply with design constraints (design rules), the error patterns may be mixed into design circuit patterns.
In order to eliminate those error patterns, it is required to specify the positions of the error patterns and correct the design layout, particularly, of the vicinities of the error patterns. However, in connection with the elimination of the error patterns, a huge amount of effort is required to correct the design layout. For this reason, it is desirable to effectively correct the design layout of the vicinities of the error patterns.